1. Field of the Invention
The present invention relates to a phase shifter that divides a frequency of an input signal to generate output signals 90 degrees out of phase with each other.
2. Description of Related Art
FIG. 11 shows the configuration of a phase shifter of the related art A phase shifter 7 of FIG. 11 receives differential clock signals, more specifically, a clock signal CLK and an inverted clock signal CLKB complementary to the clock signal CLK, divides frequencies of the signals by 2, and outputs four signals having a phase difference of 90 degrees to terminals MQ, MQB, SQ and SQB.
A dividing circuit (dividing circuit) 70 of the phase shifter 7 is configured by a master-slave type flipflop (MS-FF) where a master D latch 71 and a slave D latch 72 are connected in series. Further, an inverting Q output (QN) of the slave D latch 72 is feedback-connected to a D input (DP) of the master D latch 71, a clock signal CLK is input to a the G input (GP) of the slave D latch 72, and an inverted clock signal CLKB is input to a the G input (GP) of the master D latch 71. The thus-configured MS-FF operates as a T-flipflop where the Q output (QP) of the slave D latch 72 is inverted on the rising edge of the clock signal CLK. Thus, a divided signal having a frequency of ½ of the clock signal CLK is obtained at the Q output (QP) of the slave D latch 72. Further, on the falling edge of the clock signal CLK, the fed-back inverting Q output (QN) of the slave D latch 72 is obtained at the Q output (QP) of the master D latch 71.
Incidentally, the master D latch 71 and slave D latch 72 of FIG. 11 are generally configured as a differential circuit. FIG. 11 shows lines connected to the inverting D input (DN) and the inverting G input (GN) of the master D latches 71 and slave D latch 72.
The thus-configured dividing circuit 70 can output signals having a phase difference of 90 degrees with a frequency of ½ of the clock signal CLK to the Q output (QP) of the master D latch 71 and the Q output (QP) of the slave D latch 72 if a duty ratio of the clock signal CLK is 50%. Thus, four signals to be output to the two Q outputs (QP) of the D latches 71 and 72 and corresponding inverting Q outputs (QN) are extracted at four terminals MQ, MQB, SQ and SQB, and then the phase shifter 7 can generate four signals having a phase difference of 90 degrees. In FIG. 11, a phase of an output signal at the terminal MQ for the Q output (QP) of the master D latch 71 is set to 0 degrees as a reference phase angle, and a phase of an output signal at the terminal MQB for the inverting Q output (QN) of the master D latch 71 is set to 180 degrees, a phase of an output signal at the terminal SQ for the Q output (QP) of the slave D latch 72 is set to 90 degrees, and a phase of an output signal at the terminal SQB for the inverting Q output (QN) of the slave D latch 72 is set to 270 degrees based on the reference phase angle.
As described above, the phase shifter 7 of FIG. 11 generates output signals having a phase difference of 90 degrees on the basis of the rising edge and falling edge of the clock signal CLK. Therefore, if a duty ratio of the clock signal CLK differs from 50%, a period from the rising edge to falling edge of the clock signal CLK does not match with a period from the falling edge to rising edge of the clock signal CLK, so a phase difference between output signals of the phase shifter 7 is not 90 degrees. For example, as indicated by a waveform (a) or (b) of FIG. 12, if a duty ratio of the clock signal CLK (as indicated by solid line) and the inverted clock signal CLKB (as indicated by broken line) differs from 50%, a phase difference between two signals output to the terminals MQ and SQ is no longer 90 degrees as indicated by waveforms (c) to (f) of FIG. 12. The same holds true of a phase difference between two signals output to the terminals MQB and SQB.
Incidentally, the waveform (a) of FIG. 12 is a signal waveform for the case where a duty ratio is deteriorated due to a difference between a time width TH in a High level period of the clock signal CLK (hereinafter referred to as “High-level width”) and a time width TL in a Low level period (hereinafter referred to as “Low-level width”). On the other hand, the waveform (b) of FIG. 12 is a signal waveform for the case where a duty ratio is deteriorated due to DC offset components superimposed on at least one of the clock signal CLK and inverted clock signal CLKB. As for the waveform (b), a common voltage VCM level of the clock signals CLK and CLKB as a differential signals is changed due to the DC offset, with the result that the High-level width TH does not match with the Low-level width TL of the signals CLK and CLKB on the basis of the common voltage VCM. As a result, duty ratios of the signals CLK and CLKB differ from 50%.
There has been hitherto proposed a phase shifter capable of keeping a phase difference between output signals to 90 degrees even in such cases that the duty ratio of the clock signal CLK differs from 50% (see Japanese Unexamined Patent Publication Application Nos. 9-307414 and 8-237077, for instance).
FIG. 13 shows an example of the configuration of a phase shifter 8 as disclosed in Japanese Unexamined Patent Publication Application No. 9-307414. In FIG. 13, the dividing circuit 80 is a master-slave type T-flipflop corresponding to the dividing circuit 70 of FIG. 11. To be specific, the circuit is configured by a CML (Current Mode Logic) circuit composed of NPN-type transistors Tr1, Tr2, and Tr5 to Tr12, resistors R1 to R6, and a constant current circuit 87. Incidentally, resistor R5 and R6 are loads 82 for monitoring a duty ratio of the clock signal CLK, which are provided to convert a collector current of the signal input transistors Tr1 and Tr2 to a voltage signal. The low-pass filter (LPF) 83 extracts DC components corresponding to a difference from the 50% duty ratio of the clock signal CLK from the voltage signal converted with the duty ratio monitoring load 82. The DC components output from the LPF 83 are amplified with the DC component amplifier 84 and fed-back to base terminals of the signal input transistors Tr1 and Tr2. Incidentally, the capacitors C1 and C2 are provided to cut DC components of the input clock signal CLK and inverted clock signal and suppress an influence of a current flowing from a circuit at the previous stage of the capacitor C1 and C2 to the base of the transistors Tr1 and Tr2 and an influence of a bias voltage applied with the DC component amplifier 84 on the previous circuit.
That is, a method of controlling a phase difference between output signals used in the phase shifter 8 as disclosed in Japanese Unexamined Patent Publication Application No. 9-307414 applies DC offset to the clock signals CLK and CLKB as differential signals with the DC component amplifier 84 to adjust duty ratios of the clock signals CLK and CLKB to 50%, and generates output signals with the dividing circuit 80 based on the rising edge and falling edge of the corrected clock signal to thereby set a phase difference between output signals to 90 degrees.
Similar to the phase shifter as disclosed in Japanese Unexamined Patent Publication Application No. 9-307414, the phase shifter as disclosed in Japanese Unexamined Patent Publication Application No. 8-237077 employs a method of applying DC offset to the clock signals CLK and CLKB as differential signals to previously adjust duty ratios of the clock signals CLK and CLKB to keep a phase difference between output signals to 90 degrees. To be specific, a phase comparator detects a shift of a phase difference between output signals from 90 degrees with the phase shifter, and DC offset corresponding to the detected phase shift is fed back to an input terminal of the phase shifter. With such configuration, the phase shifter as disclosed in Japanese Unexamined Patent Publication Application No. 8-237077 keeps a phase difference between output signals to 90 degrees.
The phase shifter as disclosed in Japanese Unexamined Patent Publication Application Nos. 9-307414 and 8-237077 can keep a phase difference between output signals to 90 degrees even if a duty ratio of the clock signal differs from 50%, in the case where an input clock signal is a sine or triangular wave signal. Further, if the clock signal CLK has a rectangular wave or trapezoid wave similar to the rectangular wave, and a duty ratio of the clock signal is reduced due to the DC offset as indicated by the waveform (b) of FIG. 12, a phase difference between output signals can be kept to 90 degrees. However, phase shifter as disclosed in Japanese Unexamined Patent Publication Application Nos. 9-307414 and 8-237077 cannot adjust a duty ratio of the clock signal to 50% due to the added DC offset nor to keep a phase difference between output signals to 90 degrees if the clock signal CLK has a rectangular wave or trapezoid wave similar to the rectangular wave, and a duty ratio of the clock signal differs from 50% due to a difference between the High-level width TH and Low-level width TL as indicated by the waveform (a) of FIG. 12.
Consider the case where a trapezoid waveform that sharply rises and falls as shown in FIG. 14A and the High-level width TH is wider than the Low-level width TL by way of example. Incidentally, VCM of FIG. 14A represents a common voltage of the clock signals CLK and CLKB as differential signals. FIG. 14B shows a waveform obtained by applying DC offset to the clock signals CLK and CLKB having such waveform with the DC component amplifier 84. As is understood from FIG. 14B, even if DC offset is applied to the clock signal having a trapezoid waveform or rectangular waveform that abrupt rises as shown in FIG. 14A, it is difficult to adjust the duty ratio to 50%.
As described above, the present inventor has recognized that the phase shifter as disclosed in Japanese Unexamined Patent Publication Application Nos. 9-307414 and 8-237077 does not ensure that output signals a phase difference between which is adjusted to 90 degrees can be obtained if a duty ratio of the input clock signal cannot be adjusted to 50%.